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copyright ? anpec electronics corp. rev. a.1 - may, 2001 apw7036 www.anpec.com.tw 1 anpec reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. advanced dual pwm power controller ? ? ? ? ? 2 regulated voltage are provided ? sync switching power internal reference voltage (1.25v , 1.5v , 1.8v and 2.05v) ? async switching power internal reference voltage (1.5v) ? ? ? ? ? simple single-loop control design ? voltage-mode pwm control ? ? ? ? ? excellent output voltage regulation ? sync output : 1% over temperature ? async output : 3% over temperature ? ? ? ? ? fast transient response ? high-bandwidth error amplifier ? full 0% to 100% duty ratio ? ? ? ? ? power-good output voltage monitor ? ? ? ? ? over-voltage and over-current fault monitors ? ? ? ? ? small converter size ? constant frequency operation(200khz) ? programmable oscillator from 50khz to 800khz ? reduce external component count ? ? ? ? ? 20pin , soic package features applications ? ? ? ? ? high power 5v to 2.5 or 3.3v dc-dc regulator ? ? ? ? ? vga card power regulation general description the apw7036 provides complete power control and protection for two dc-dc converter optimized in vga card applications. it integrates two pwm controllers , as well as the monitoring and protection function into a single package. the apw7036 provides simple , single feedback loop , voltage mode control with fast transient response. the output voltage of the sync converter can be pre- cisely regulated to as low as v ref (1.25v , 1.5v , 1. 8v and 2.05v) , with a maximum tolerence of 1.0% over temperature. the apw7036 can provides in excess of 14a of out- put current for an on-board dc/dc converter. it can monitors all the output voltage , and a single power good signal is issued when the sync output is within 10 % of the v ref setting and the async output lev- els is above under-voltage levels. additional built-in over-voltage protection for the sync output uses the lower mosfet to prevent output voltage above 115 % of the v ref setting. the pwm controller?s over-cur- rent function monitor the output current by sensing the voltage drop across the upper mosfet?s r ds(on) , eliminating the need for a current sensing resistor . pin description vcc gate phase2 fb2 ocset1 fb1 comp ocset2 pgood ss vsen nc vaux 1 2 3 4 5 6 7 8 10 9 16 15 14 13 gnd pgnd nc 17 18 19 20 12 11 ugate lgate phase1 fault/rt
copyright ? anpec electronics corp. rev. a.1 - may, 2001 apw7036 www.anpec.com.tw 2 ordering information absolute maximum ratings symbol parameter rating unit vcc supply voltage 15 v v i , v o input , output or i/o voltage gnd -0.3 v to v12 +0.3 v t a operating ambient temperature range 0 to 70 c t j junction temperature range 0 to 125 c t stg storage temperature range -65 to +150 c t s soldering temperature 300 ,10 seconds c block diagram gate control soft-start and fault logic gate control ocset2 gate phase2 fb2 gnd pgnd lgate phase1 ugate pgood ocset1 vsen fb1 ss fault 200ua vcc drive2 oc2 inhibit pwm2 1.5v error amp2 1.05v vcc oscillator 4.5v v ref error amp1 0v fault oc1 pwm1 vcc lower drive vcc drive1 inhibit 115% 90% 110% 200ua comp 28ua por vaux vcc apw7036 v ref voltage code 12 : 1.25v 15 : 1.50v 18 : 1.80v 20 : 2.05v package code k : sop - 20 temp. range c : 0 to 70 c handling code tu : tube tr : ta p e & reel handling code temp. range package code v ref voltage code
copyright ? anpec electronics corp. rev. a.1 - may, 2001 apw7036 www.anpec.com.tw 3 thermal characteristics symbol parameter value unit r ja thermal resistance in free air soic soic (with 3in 2 of copper) 75 65 c/w electrical characteristics (recommended operating conditions , unless otherwise noted) refer to block and simplified power system diagrams , and typical application schematic apw7036 symbol parameter test conditions min. typ. max. unit v cc supply current i cc nominal supply current ugate , lgate , gate , open 9ma power-on reset rising vcc threshold vocset=4.5v 10.4 v falling vcc threshold vocset=4.5v 8.2 v rising vaux threshold vocset=4.5v 2.5 v vaux threshold hysteresis vocset=4.5v 0.5 v rising v ocset threshold 1.26 v oscillator f ocs free running frequency rt= open 185 200 215 khz ? v osc ramp amplitude rt= open 1.9 v p-p switching controller reference voltage v ref reference voltage apw7036-12 apw7036-15 apw7036-18 apw7036-20 1.25 1.50 1.80 2.05 v reference voltage accuracy -1.0 +1.0 % v fb2 reference voltage 1.5 v reference voltage accuracy -3.0 +3.0 % synchronous pwm controller error amplifier dc gain 88 db gbwp gain-bandwidth product 15 mhz sr slew rate comp=10pf 6 v/ s pwm controllers gate drivers i ugate ugate1,gate source v cc =12v, v ugate 1,gate =6v 1 a r ugate ugate1,gate sink v ugate1,gate =1v 3.5 ?
copyright ? anpec electronics corp. rev. a.1 - may, 2001 apw7036 www.anpec.com.tw 4 electrical characteristics cont. functional pin description ugate (pin 1) connect ugate pin to the synchronous pwm converter?s upper mosfet gate. this pin provides the gate drive for the upper mosfet. vcc (pin 2) provide a 12v bias supply for the ic to this pin. this pin also provides the gate bias charge for all the mosfets controlled by the ic. the voltage at this pin is monitored for power-on reset purposes. gate (pin 3) connect gate pin to the standard buck pwm converter?s mosfet gate. this pin provides the gate drive for the mosfet. phase2 (pin 4) connect the phase2 pin to the standard buck pwm converter?s mosfet source. this pin is used to moni- tor the voltage drop across the mosfet for over-cur- rent protection. pgood (pin 5) pgood is an open collector output used to indicate the status of the output voltages. this pin is pulled low when the synchronous regulator output is not within 10% of the reference voltage or the other output is below under-voltage thresholds. nc (pin 10, 13) no connection. ocset1 , 2 (pin 17 , 6) connect a resistor (r ocset ) from this pin to the drain of the pwm converter?s mosfet. r ocset , an internal 200 a current source (i ocset ) , and the mosfet?s on-resistance(r ds(on) ) set the converter over-current apw7036 symbol parameter test conditions min. typ. max. unit pwm controllers gate drivers i lgate lgate source v cc =12v, v lgate =1v 1 a r lgate lgate sink v lgate = 1v 3 ? protection vsen over-voltage (vsen/v ref ) vsen rising 115 120 % i ovp fault souring current v fault/rt =2.0v 8.5 ma i ocset ocset1,2 current source v ocset = 4.5v dc 170 200 230 a i ss soft start current 28 a power good vsen upper threshold (vsen/ v ref ) vsen1 rising 110 % vsen under voltage (vsen/v ref ) vsen1 rising 94 % vsen hysteresis (vsen/ v ref ) upper /lower threshold 2 % v pgood pgood voltage low i pgood = -4ma 0.8 v
copyright ? anpec electronics corp. rev. a.1 - may, 2001 apw7036 www.anpec.com.tw 5 functional pin description cont. (oc) trip point according to the following equation: i peak = an over-current trip cycles the soft-start function. fb2 (pin 7) this pin provides the feedback for the non-synchro- nous switching regulator. a resistor driver is con- nected from this pin to regulator output and gnd that sets the output voltage. the value of the resistor con- nected from regulator output to fb2 must be less than 150 ? . ss (pin 8) connect a capacitor from this pin to ground. this capacitor , along with an internal 28 a current source , sets the soft-start interval of the converter. fault / rt (pin 9) this pin provides oscillator switching frequency adjustment. by placing a resistor (r t ) from this pin to gnd , the nominal 200khz switching frequency is increased. conversely , connecting a pull-up resistor (r t ) from this pin to vcc reduces the switching frequency. nominally , the voltage at this pin is 1.26v. in the event of an over-voltage or over-current condition , this pin is internally pulled to vcc. vaux (pin 11) the +3.3v input voltage at this pin is monitored for power-on reset (por) purposes. gnd (pin 12) signal ground for the ic. all voltage levels are mea- sured with respect to this pin. comp and fb1 (pins 14 , and 15) comp and fb1 are the available external pins of the synchronous pwm regulator error amplifier. the fb1 pin is the inverting input of the error amplifier. simi- larly , the comp pin is the error amplifier output. these pins are used to compensate the voltage-mode con- trol feedback loop of the synchronous pwm converter. vsen (pin 16) this pin is connected to the synchronous pwm converters?s output voltage. the pgood and ovp comparator circuits use this signal to report output voltage status and for over-voltage protection. pgnd (pin 18) this is the power ground connection. tie the syn- chronous pwm converter?s lower mosfet source to this pin. lgate (pin19) connect lgate to the synchronous pwm converter?s lower mosfet gate. this pin provides the gate drive for the lower mosfet. phase1 (pin 20) connect the phase1 pin to the synchronous pwm converter?s upper mosfet source. this pin is used to monitor the voltage drop across the upper mosfet for over-current protection. i ocset * r ocset r ds(on)
copyright ? anpec electronics corp. rev. a.1 - may, 2001 apw7036 www.anpec.com.tw 6 simplified power system diagram typical characteristics apw7036 +5 v in q1 q2 q3 synchronous pwm controller standard buck pwm controller v out2 v out1 +5v vout2 (3.3v) vout1 (2.5v) +5v +12v c10 330uf r12 1.2k c8 220pf r13 5.1r q2 apm9410 d1 fm5800 r9 120rf c11 330uf r10 100rf r7 3k r4 5.1r q1b apm7313 c5 330uf c4 330uf c3 330uf l2 7.8uh q1a apm7313 c2 220pf r2 1.2k r3 5.1r c1 1uf r1 10r l3 7.8uh l1 1uh c6 10pf c2 2700pf r6 100rf r5 67rf r8 150k 1 10 9 8 7 6 5 4 3 2 20 11 12 13 14 15 16 17 18 19 ugate ocset2 pgood phase2 gate vcc nc ss fb2 fault gnd fb1 comp nc vaux pgnd ocset1 vsen lgate phase1 apw7036-15 lp1 led r11 750 +5v c9 0.1uf +3.3v
copyright ? anpec electronics corp. rev. a.1 - may, 2001 apw7036 www.anpec.com.tw 7 typical characteristics v ref voltage deviation (%) junction temperature ( o c) junction temperature ( o c) v fb2 reference voltage deviation (%) -1.0% -0.8% -0.6% -0.4% -0.2% 0.0% 0.2% 0.4% 0.6% 0.8% 1.0% 0 102030405060708090100 -1.0% -0.8% -0.6% -0.4% -0.2% 0.0% 0.2% 0.4% 0.6% 0.8% 1.0% 0 102030405060708090100 note : the referance voltage(v ref ) deviation is v ref (t j ) - v ref (25 o c) v ref (25 o c) x 100% switching frequency ( khz ) 1 10 100 1000 10000 50 150 250 350 450 550 650 750 rt ( k ? ) rt pull down to gnd to +12v rt pull up
copyright ? anpec electronics corp. rev. a.1 - may, 2001 apw7036 www.anpec.com.tw 8 package information so ? 300mil ( reference jedec registration ms-013) millimeters variations- d inches variations- d dim min. max. variations min. max. dim min. max. variations min. max. a2.35 2.65 so-16 10.10 10.50 a 0.093 0.1043 so-16 0.398 0.413 a1 0.10 0.30 so-18 11.35 11.76 a1 0.004 0.0120 so-18 0.447 0.463 b 0.33 0.51 so-20 12.60 13 b 0.013 0.020 so-20 0.496 0.512 d see variations so-24 15.20 15.60 d see variations so-24 0.599 0.614 e 7.40 7.60 so-28 17.70 18.11 e 0.2914 0.2992 so-28 0.697 0.713 e 1.27bsc so-14 8.80 9.20 e 0.050bsc so-14 0.347 0.362 h 10 10.65 h 0.394 0.419 l 0.40 1.27 l 0.016 0.050 n see variations n see variations 10 8 10 8 n 12 3 e h d l gauge plane 1 e b a1 a
copyright ? anpec electronics corp. rev. a.1 - may, 2001 apw7036 www.anpec.com.tw 9 classification reflow profiles package reflow conditions refolw condition (ir/ convection or vpr reflow) physical specifications terminal material solder-plated copper (solder material : 90/10 or 63/37 snpb) lead solderability meets eia specification rsi86-91, ansi/j-std-002 category 3. packaging 1000 devices per reel convection or ir/ convection vpr average ramp-up rate(183 c to peak) 3 c/second max. 10 c /second max. preheat temperature 125 25 c) 120 seconds max. temperature maintained above 183 c 60 ~ 150 seconds time within 5 c of actual peak temperature 10 ~ 20 seconds 60 seconds peak temperature range 220 +5/-0 c or 235 +5/-0 c 215~ 219 c or 235 +5/-0 c ramp-down rate 6 c /second max. 10 c /second max. time 25 c to peak temperature 6 minutes max. pkg. thickness 2.5mm and all bags pkg. thickness < 2.5mm and pkg. volume 350 mm3 pkg. thickness < 2.5mm and pkg. volume < 350mm3 convection 220 +5/-0 c convection 235 +5/-0 c vpr 215-219 c vpr 235 +5/-0 c ir/convection 220 +5/-0 c ir/convection 235 +5/-0 c reference jedec standard j-std-020a april 1999 pre-heat temperature 183 c peak temperature time temperature
copyright ? anpec electronics corp. rev. a.1 - may, 2001 apw7036 www.anpec.com.tw 10 tape & reel dimensions reliability test program test item method description solderability mil-std-883d-2003 245 c , 5 sec holt mil-std-883d-1005.7 1000 hrs bias @ 125 c pct jesd-22-b, a102 168 hrs, 100 % rh , 121 c tst mil-std-883d-1011.9 -65 c ~ 150 c, 200 cycles esd mil-std-883d-3015.7 vhbm > 2kv, vmm > 200v latch-up jesd 78 10ms , i tr > 100ma t ao e w po p ko bo d1 d f p1 a j b t2 t1 c application a b c j t1 t2 w p e sop-20 330 162 1.5 12.75 0.15 2 + 0.6 24.4 +0.2 2 0.2 24 + 0.3 - 0.1 12 0.1 1.75 0.1 application f d d1 po p1 ao bo ko t sop-20 11.5 0.1 1.5+0.1 1.5+0.25 4.0 0.1 2.0 0.1 8.2 0.1 13 0.1 2.5 0.1 0.35 0.013 (mm)
copyright ? anpec electronics corp. rev. a.1 - may, 2001 apw7036 www.anpec.com.tw 11 cover tape dimensions customer service carrier width 24 cover tape width 21.3 anpec electronics corp. head office : 5f, no. 2 li-hsin road, sbip, hsin-chu, taiwan, r.o.c. tel : 886-3-5642000 fax : 886-3-5642050 taipei branch : 7f, no. 137, lane 235, pac chiao rd., hsin tien city, taipei hsien, taiwan, r. o. c. tel : 886-2-89191368 fax : 886-2-89191369

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